Field of the Invention
The invention is directed to a method for estimating stress of an electronic component and more particularly, to a method for estimating propagating stress of an electronic component.
Description of Related Art
In a semiconductor packaging process, a chip is commonly disposed on a substrate, and conductive bumps (e.g., solder balls) are often used as a bonding medium for the chip and the substrate. Although the bonding method using the conductive bumps has low cost and is easy for manufacturing, coefficients of thermal expansion (CTEs) of bonding surfaces are different. Fatigue effect resulted from repetitive changes in temperature or voltage during system operation is mainly the reason for damage to bonding points of the chip. Fatigue failure may be classified into mechanical fatigue failure and thermal fatigue failure. Mechanical fatigue failure is due to continuous transformation and movement, resulting in a decrease in mechanical strength. Thermal fatigue failure, on the other hand, is caused by poor match of coefficients of thermal expansion between two surfaces, resulting in the two surfaces pulling each other because of minor transformation generated at high and low temperatures, which, under long term influences, may easily cause the surfaces to peel off. As such, both the chip and the substrate under the chip would be damaged, which leads to the reduction in effectiveness and reliability of the chip package structure.
Accordingly, a stress generated to each conductive bump under a certain temperature or voltage variation condition in the semiconductor package is commonly calculated by utilizing finite element simulation at present, so as to estimate a lifetime of each conductive bump. However, the finite element simulation has a complicated calculation process and consumes much computing time. Therefore, how to rapidly estimate the stress and lifetime of each conductive bump in the semiconductor package has become an important subject in the art.